As a Strategic member of RISC-V International, Tiempo Secure will secure and integrate processors implementing the RISC-V open standard instruction set architecture (ISA) into its TESIC Secure Element IP, thus easing integration for its customers; in addition, Tiempo Secure will bring its recognized security expertise to the RISC-V community.
By becoming a Strategic Member of RISC-V International, Tiempo Secure expands its offer with a new RISC-V processor core based TESIC Secure Element, implementing the RISC-V instruction set architecture specification “RV32IMCB.” This evolution will bring decisive advantages to the Tiempo Secure offering: while keeping the current offer with a proprietary CPU, the new CPU provides a modern, industry standard, 32 bit solution. With this move, Tiempo Secure adopts a standard architecture that will make integration and development easier for their customers, benefiting from the extensive pool of RISC-V specialists. The adoption of the RISC-V architecture will allow integrators and software developers for Tiempo Secure TESIC products to use standard development tools, making the integration of its TESIC products faster and easier.
As Tiempo Secure is a well-established security expert, its TESIC Secure Element IP products are certification ready. Tiempo Secure TESIC Secure element IP has been integrated into System-on-Chips that have passed Common Criteria EAL 5+ certification. Also, Tiempo Secure commits to bringing extensive support to its integrators ensuring that they obtain security certification.
RISC-V International is the global non-profit home of the open standard RISC-V Instruction Set Architecture (ISA), related specifications, and stakeholder community.Hardware implementations support the RISC-V open instruction set, making it easy for integrators to develop software and to port it between different types of hardware. As RISC-V is widely adopted, numerous software tools are available and the developer community is extensive.
Serge Maginot, Tiempo Secure CEO, said: “Joining RISC-V International represents a milestone in the history of Tiempo Secure. Not only will we be able to keep on delivering secure products to our customers, but we are now making it even easier for them to implement our products into their own System-on-Chips and software.”
Calista Redmond, CEO of RISC-V International, adds: ”We are glad to see Tiempo Secure join RISC-V International. Their background in Secure Element IP development, and more globally its security expertise will represent a valuable stakeholder for our organization and members.”
About Tiempo Secure
Tiempo Secure (tiempo-secure.com) is an independent SME headquartered near Grenoble, France, founded in 2007, with customers in Europe, North America and Asia. They specialize in the development of intellectual property (IP) in microelectronics and in embedded software for securing connected objects.
The company offers a wide range of Secure Elements (TESIC family) ready to be integrated into “System-on-Chip” (SoC) components, and allowing maximum security (Common Criteria EAL5+ certified) of connected components: authentication on networks with integrated SIM (iSIM/iUICC), payment (EMVCo), government or private identification, web authentication (FIDO 2), smart car access, communication with autonomous vehicles (V2X HSM).
About RISC-V International
RISC-V International (riscv.org) is the non-profit home of the open standard RISC-V Instruction Set Architecture (ISA), related specifications, and stakeholder community. More than 3,100 RISC-V members across 70 countries contribute and collaborate to define RISC-V open specifications as well as convene and govern related technical, industry, domain, and special interest groups. RISC-V combines a modular technical approach with an open, royalty-free license model meaning that anyone, anywhere can benefit from the IP contributed and produced by RISC-V. RISC-V enables the community to share technical investment, contribute to the strategic future, create more rapidly, enjoy unprecedented design freedom, and substantially reduce the cost of innovation.
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