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Imec Demonstrates Backside Power Delivery with Buried Power Rails for Back and Frontside Routing - Standard cell scalability and power performance improvement for 2D and 3D ICs are highlighted as key benefits - imec-int.com
Imec Demonstrates Backside Power Delivery with Buried Power Rails for Back and Frontside Routing

 

NewswireToday - /newswire/ - Leuven, Belgium, 2022/06/14 - Standard cell scalability and power performance improvement for 2D and 3D ICs are highlighted as key benefits - imec-int.com.

   
 
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This week, at the 2022 IEEE VLSI Symposium on Technology and Circuits (vlsisymposium.org), imec, a world-leading research and innovation hub in nanoelectronics and digital technologies, presents the first experimental demonstration of a routing scheme for logic ICs with backside power delivery enabled through nano-through-silicon-vias (nTSVs) landing on buried power rails (BPRs). The BPRs connect to scaled FinFET devices whose performance was not impacted by backside wafer processing. The novel routing scheme with decoupled power and signal wiring acts as a scaling booster for future logic technologies (2nm and beyond). It also offers a system performance benefit by improving the power delivery. Additionally, imec demonstrated a performance boost by implementing a 2.5D MIMCAP in the backside.

The concept of backside power delivery allows to decouple the power delivery network from the signaling metallization scheme in logic ICs, hence alleviating routing congestion in the backof-line and delivering a power performance benefit. Since imec’s first announcement in 2019, different implementations have been proposed. At VLSI 2021, for example, imec for the first time showed backside connectivity through nTSVs landing on metal-1 pads in the wafer’s frontside.

At this year’s VLSI, in the paper by A. Veloso et al., imec demonstrates an advanced integration scheme with scaled FinFET devices connecting to both backside and frontside through buried power rails a world’s first. Naoto Horiguchi, Director CMOS Device Technology at imec: “We believe that combining backside power delivery with buried power rails a structural scaling booster in the form of a local power rail that is buried deep in the chip’s frontof-line is the most promising implementation scheme of a backside power delivery network in terms of scalability and performance.”

“With our test vehicle, in which nTSVs land on buried power rails defined in the wafer’s frontside, we show that the performance of the FinFETs is not degraded by backside processing”, adds Naoto Horiguchi. “This includes bonding of the wafer to a carrier wafer, wafer backside thinning and processing of ~320nm deep nTSVs. The nTSVs land on BPRs with tight overlay control and are implemented at a tight pitch of 200nm without consuming any area of the standard cell. This ensures further scalability of the technology towards 2nm and beyond.”

At the system level, backside power delivery promises to improve the overall power delivery performance, which increasingly suffers from a rise in power density and aggressive supply-voltage (or IR) drop. Eric Beyne, VP R&D of imec’s 3D System Integration: “In a 2022 VLSI paper by R. Chen et al., we combined backside processing with the implementation of a 2.5D (i.e., pillar-like) metal-insulator-metal capacitor (MIMCAP), which serves as a decoupling capacitor. The 2.5D MIMCAP boosts capacitance density with a factor of 4 to 5x, allowing a further improvement of the IR drop (32.1%/23.5% over the no-MIMCAP/2D-MIMCAP counterparts, respectively). The results are derived from an IR drop modelling framework calibrated with experimental data.”

Eric Beyne: “Our work shows that the backside can create a very dynamic design space with new design options that can help address shortcomings of traditional 2D IC scaling. In addition, we have shown its validity for 3D system scaling technologies, where the carrier wafer in de bonding process is replaced with a functional wafer (e.g., a logic wafer for enabling logic-on-logic 3D-SOCs), and the bottom dies are powered from the backside.”

About imec

Imec (imec-int.com) is a world-leading research and innovation center in nanoelectronics and digital technologies. Imec leverages its state-of-the-art R&D infrastructure and its team of more than 5,000 employees and top researchers, for R&D in advanced semiconductor and system scaling, silicon photonics, artificial intelligence, beyond 5G communications and sensing technologies, and in application domains such as health and life sciences, mobility, industry 4.0, agrofood, smart cities, sustainable energy, education, … Imec unites world-industry leaders across the semiconductor value chain, Flanders-based and international tech, pharma, medical and ICT companies, start-ups, and academia and knowledge centers. Imec is headquartered in Leuven (Belgium), and has research sites across Belgium, in the Netherlands and the USA, and offices in China, India, Taiwan and Japan. In 2021, imec's revenue (P&L) totaled 732 million euro.

Imec is a registered trademark for the activities of imec International (IMEC International, a legal entity set up under Belgian law as a “stichting van openbaar nut”), imec Belgium (IMEC vzw supported by the Flemish Government), imec the Netherlands (Stichting IMEC Nederland), imec Taiwan (IMEC Taiwan Co.), imec China (IMEC Microelectronics (Shanghai) Co. Ltd.), imec India (IMEC India Private Limited), imec San Francisco (IMEC Inc.) and imec Florida (IMEC USA Nanoelectronics Design Center Inc.).

 
 
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Imec Demonstrates Backside Power Delivery with Buried Power Rails for Back and Frontside Routing

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