NewswireToday - /newswire/ -
Zhuhai, Guangdong, China, 2009/06/17 - EBR-1533 is the Enhanced Bit Rate version of MIL-STD-1553A/B, which is defined by SAE according to MIL-STD-1553B standard.
Different from MIL-STD-1553B bus, EBR-1553 applies star-topology and use RS485 as physical layer. Except the RT to RT message format, EBR-1553 supports all the other message formats defined by MIL-STD-1553B.
Since EBR-1553 applies start-topology, a HUB should be used to route messages from an RT to the BC or from the BC to an RT. AS5652 defines three types of HUBs, “SPEC” mode “SWITCH” mode and “LINK” mode.
Under SPEC mode, BC sends the message to all of the RTs, and then monitors the Tx data line of all the RTs’. The same with MIL-STD-1553B, when a command word received, an RT would only response the command word which contains its own address in the RT address field.
Under SWITCH mode, BC assign each node with an universal address, ranging from 0 to 31. For each RT, it should be placed at the designated node, which the address is the same with the RT. For example, the RT 8 should only be placed at the node 8. Unlike the SPEC mode, under SWITCH mode, the BC only send the message to the RT addressed by the command word.
The address field of the command word will no make any sense, when the HUB work under LINK mode. The BC will only send the command to the RT intended. For example, if the BC want to send a command to RT8, it’ll only send the command to the node 8, the address field of the command word is all zero, and the RT8 will response to all the incoming command except the broadcast.
Zhuhai Microsis Electronic Technology Co., Ltd (microsis.cn) has developed two IP cores, FBIP1511 and FBIP1512, which could provide total EMR-1553 solution. FBIP1511 is a Bus Controller IP core with a built-in SWITCH mode HUB, and up to 32 RTs and 1 BM could be connected. FBIP1512 is a RT/BM IP core with 1 RT and 1 BM. The function and register operation of FBIP151X is compatible with BU6158X.
FBIP151X could be implemented in ALTERA CYCLONEI/II/II FPGA, achieving 160Mhz sampling clock that makes the Codec more stable and reliable.