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Atrenta Presents Expanded RTL Signoff Platform at 52nd DAC - Atrenta, Inc. announced that it will present key new additions to its RTL Signoff platform at the 52nd Design Automation Conference to be held June 7-11 at Moscone Center in San Francisco, California - Atrenta.com
Atrenta Presents Expanded RTL Signoff Platform at 52nd DAC

 

NewswireToday - /newswire/ - San Jose, CA, United States, 2015/06/05 - Atrenta, Inc. announced that it will present key new additions to its RTL Signoff platform at the 52nd Design Automation Conference to be held June 7-11 at Moscone Center in San Francisco, California - Atrenta.com.

   
 
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Atrenta, Inc., the leading provider of SoC Realization solutions for the semiconductor and consumer electronics industries, today announced that it will present key new additions to its RTL Signoff platform at the 52nd Design Automation Conference to be held June 7-11, 2015 at Moscone Center in San Francisco, California. Atrenta’s RTL Signoff platform, built on its industry leading SpyGlass®, BugScope® and GenSys® tools, enables efficient verification and optimization of SoCs early in the design cycle, thus minimizing time to design closure and avoiding critical chip failures.

While SoCs are becoming bigger and more complex, the use of advanced process nodes has made RTL Signoff a design imperative. At DAC, Atrenta will showcase how its RTL Signoff platform has been expanded to address these challenges. Some key highlights are:

SpyGlass Platform

• Next generation, SpyGlass Turbo that is “Smarter, Faster, and Deeper”
• IP Signoff solution with a broader industry adoption and hooks for SoC integration
• Seamless Clock Domain Crossing (CDC) flow for FPGA designs
• Static SoC connectivity verification
• CDC verification for RTL and netlist including structural, functional and hierarchical methods
• Reset Domain Crossing (RDC) verification
• Timing constraint management including equivalence, propagation and timing exception verification
• An integrated platform for RTL power estimation, optimization, and verification
• Hard-to-test fault analysis at RTL for manufacturing test

GenSys Platform for chip assembly, surgical RTL generation, and SDC restructuring

BugScope Apps for progressive functional / code coverage tracking, and automatic assertion generation for SoC simulation and emulation
For a complete listing of suite sessions at the Atrenta DAC booth #1732, please visit: atrenta.com/DAC2015/sessions.php

“It was two years ago at DAC that we launched our RTL Signoff platform, and the response from our 280+ customers has been overwhelmingly positive,” said Piyush Sancheti, vice president of marketing at Atrenta. “We have continued to expand the scope of our RTL platform to address the next set of SoC challenges of scale, complexity, and advanced process nodes. We look forward to sharing our progress with prospects, customers, and partners at DAC.”

In addition to show floor activities, Atrenta will be featured in 11 Designer Track papers and posters, where customers share their experience using Atrenta products to solve critical design challenges. Atrenta will also participate in a Sunday DAC workshop on Enterprise-Level IP Management. For the 7th year in a row, Atrenta, as the founding sponsor for the “I Love DAC” campaign, has provided users with free access to DAC. Atrenta is also a top sponsor for the “Stars of IP Party” hosted by IP-Extreme and the “Love IP Party at DAC” hosted by Heart of Technology.

About Atrenta, Inc.
Atrenta's SpyGlass Predictive Analyzer® (atrenta.com) significantly improves design efficiency for the world's leading semiconductor and consumer electronics companies. Patented solutions provide early design insight into the demanding performance, power and area requirements of the complex system on chips (SoCs) fueling today's consumer electronics revolution. More than two hundred eighty companies and thousands of design engineers worldwide rely on SpyGlass to reduce risk and cost before traditional EDA tools are deployed. With the addition of GenSys® and BugScope®, RTL modification and verification efficiency are also enhanced, allowing engineers and managers to find the fastest and least expensive path to silicon for complex SoCs.

SpyGlass from Atrenta: Insight. Efficiency. Confidence.

© 2015 Atrenta Inc. All rights reserved. Atrenta, the Atrenta logo, SpyGlass, SpyGlass Predictive Analyzer, GenSys and BugScope are registered trademarks of Atrenta Inc. All others are the property of their respective holders.

This press release contains forward-looking statements. Atrenta disclaims any obligation and does not undertake to update or revise the forward-looking statements in this release.

 
 
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Written by / Agency / Source: SpyGlass® / Atrenta, Inc.

 
 

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Atrenta Presents Expanded RTL Signoff Platform at 52nd DAC

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Atrenta, Inc. | 52nd DAC
Publisher Contact: Danielle Arnold - Atrenta.com 
408-453-3333 danielle[.]atrenta.com
 
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IMPORTANT INFORMATION: Issuance, publication or distribution of this press release in certain jurisdictions could be subject to restrictions. The recipient of this press release is responsible for using this press release and the information herein in accordance with the applicable rules and regulations in the particular jurisdiction. This press release does not constitute an offer or an offering to acquire or subscribe for any SpyGlass® / Atrenta, Inc. securities in any jurisdiction including any other companies listed or named in this release.

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