The new Verification IP (VIP) reduces testbench assembly time for ASIC (application-specific integrated circuit) and FPGA (field-programmable gate array) design verification by a factor of up to 10X.
Verification IP is intended to help engineers reduce the time spent building testbenches by providing re-usable building blocks for common protocols and architectures. However, even standard protocols and common architectures can be configured and implemented differently from design to design. As a result, traditional VIP components can take days, or even weeks, to prepare for a simulation or emulation testbench.
“When designing with the ARMv8-A architecture and ARM® CoreLink™ cache coherent interconnects in mobile, networking and server SoCs, our partners have a choice of PCIe root complex solutions,” said Jim Wallace, director, systems and software group, ARM®. “ARM® has used Mentor’s PCIe VIP library running on Questa® and Veloce® to help verify critical interactions between PCIe and ARM® AMBA® interface domains to enable rapid deployment and accurate protocol checking.”
Unlike traditional verification IP, Mentor’s new PCIe EZ-VIP is “design-aware,” eliminating several time-consuming steps in the testbench assembly process. This fast-forwards verification engineers past tedious configuration and implementation set-up tasks, directly to high-value scenario generation, reducing a process that used to take days or weeks to just hours.
“We have been pleased to collaborate with Mentor to support the validation of PCIe EZ-VIP,” said Stephane Hauradou, CTO of PLDA. “After being one of the first PCIe providers to very quickly develop and introduce PCIe 3.0 and PCIe 4.0 controllers to ASIC and verification engineers, PLDA is pleased to combine silicon proven XpressRICH3 and XpressRICH4 IPs with PCIe EZ-VIP as a reliable, highly configurable and easy-to-use complete solution for ASIC project teams.”
“Having easy-to-use, pre-qualified PCIe Verification IP is very important for our customers. We have worked with Mentor to help them validate their PCIe EZ-VIP with our Expresso 3.0 core,” said Brian Daellenbach, president of Northwest Logic. “Consequently, customers can use the Mentor PCIe VIP with our silicon-proven PCI Express cores to create and verify their designs with high confidence.”
Mentor’s PCIe EZ-VIP includes pre-packaged, easy-to-use verification environments for the serial and parallel interfaces of PCIe 1.0, 2.0, 3.0, 4.0 and mPCIe, which can be used to verify PHY, Root Complex and Endpoint designs. Test plans, compliance tests, test sequences, and protocol coverage are all included as SV and XML source code, allowing simple re-use, extension and debug. The Mentor VIP components also include a comprehensive set of protocol checks, error injection and debug capabilities.
Mentor Graphics, Mentor, Questa and Veloce are registered trademarks of Mentor Graphics Corporation. All other company or product names are the registered trademarks or trademarks of their respective owners.
About Mentor Graphics
Mentor Graphics Corporation (mentor.com) is a world leader in electronic hardware and software design solutions, providing products, consulting services and award-winning support for the worlds most successful electronic, semiconductor and systems companies. Established in 1981, the company reported revenues in the last fiscal year in excess of $1.15 billion. Corporate headquarters are located at 8005 S.W. Boeckman Road, Wilsonville, Oregon 97070-7777.